1. Field of the Invention
The invention relates in general to a self-synchronizing descrambler for descrambling a signal having a period of 2.sup.n-1 bits where the output of at least one shift register stage is connected to the input of a modulo-2 adder.
2. Description of the Prior Art
In digital signal transmission pulse patterns can occur which have a disturbing DC component or whose energy component is particularly high at specific discrete frequencies. So as to avoid these pulse patterns, the digital signal which is to be transmitted is scrambled at the transmitting end by modulo-2 addition with a pseudo-random sequence. At the receiving end, descrambling is effected with a further modulo-2 addition with the pseudo-random sequence which has previously been used at the transmitting end. The next synchronization of the pseudo-random generators used at the transmitting and receiving ends can be avoided by the use of free running, multiplicative or self-synchronizing scramblers and descramblers.
The continued development of the digital telecommunication network has necessitated between central points of the network transmission devices for signals of very high transmission speeds. This results in the need to construct scramblers and descramblers for digital signals of a very high clock frequency.
The Siemens Research and Development reports Volume 6, (1977) No. 1, pages 1 through 5 discloses the possibility of constructing descramblers for digital signals of very high clock frequencies. The digital signals are scrambled in a plurality of parallel channels with a correspondingly lower bit repetition frequency and the signals which are formed are combined by multiplexers. The receiving apparatus is similarly constructed where following a demultiplexer parallel descrambling in a plurality of channels occurs. In addition to the high outlay, this results in the necessity to synchronize multiplexer and demultiplexer to each other.
Governmental authorities have standardized scrambling for the individual hiearchy stages of the digital long range network. Thus, for example, in the CCITT recommendations under V27b of the International Postal Authorities there has been prescribed a scrambler having a scrambling period of 127 bits and a corresponding descrambler.